1. Field of the Invention
This invention relates, in one embodiment, to a process for identifying the location of potential transient defect sites on an integrated circuit chip on a substrate, where defects are most likely to occur, forming a file containing the locations of such transient defect sites, converting the file into a CAD image layer capable of displaying the location of such potential transient defects, and displaying such potential transient defects as a CAD image layer superimposed over a CAD image of the actual circuit to permit visual inspection of the resulting compound CAD image, and to permit optional action to be taken in view of such potential transient defects. In another embodiment of the invention, the file containing the locations of the potential transient defects is transmitted to a critical dimension (CD) scanning electron microscope (SEM) which monitors the potential transient defect addresses during processing of the chip. The two embodiments of the invention may be practiced in the alternative or in combination with one another.
2. Description of the Related Art
Conventionally, in the formation of integrated circuit chips from a semiconductor substrate such as, for example, a silicon substrate, test patterns have been formed in “scribe” areas on the semiconductor substrate (i.e., the regions where the substrate will be cut or “scribed” into chips). Such test patterns usually include, for example, the finest pattern such as a line which will be used in the formation of the integrated circuit structure, since the formation of such patterns sometimes presents the most challenging areas to lithographically resolve. Actual device components or features such as contacts, vias, gates, etc., have also been identified as sites for critical dimension (CD) locations. However, these locations are not always the most challenging sites to measure due to other factors such as, for example, unforeseen behavior of resolution enhancement treatments wherein the reticle (mask) is deliberately modified to form the desired mask image size in the photoresist layer.
Furthermore, as dimensions of all features in an integrated circuit structure have become smaller and smaller, to a size range where the dimensions of the feature are sometimes smaller than the wavelength of the light used to project the image, it has become more difficult to predict, by planar dimensions (length and width) alone, e.g., by the accuracy of the lithographic reproduction of the width of a thin line, what part of a design will be the most difficult to resolve.
It is known to analyze an integrated circuit chip for the presence of non-repeating defects such as a scratch or a particle, missing portions of a pattern or added pattern. Commercial equipment is available to conduct such inspections of an integrated circuit chip. For example, such commercial integrated circuit inspection equipment is available from KLA-Tencor, the assignee of this invention, under the names, 2351, 2360, and 2370, to identify and provide the location of such defects. However, it is not known to use such commercially available equipment for identification, analysis, and display of sites where defects might occur, i.e., “transient defects”, or for mapping the location of such sites on the chip, or for measuring the critical dimensions of such sites.
It would, therefore, be desirable to provide a process wherein transient defects would be identified, the locations of such transient defects mapped, and the effect of location and size of each of the potential transient defects would be visually displayed and monitored on each chip to determine whether or not measures should be taken to remedy possible occurrence of the transient defect.